This invention pertains to semiconductor patterning processes. More particularly, it pertains to apparatus and methods for monitoring the fidelity of patterns produced by patterning processes, such as photolithography and etching processes that are used to pattern semiconductor materials.
A typical semiconductor product device is formed from a number of product features residing and coupled together within multiple semiconductor layers. Each layer will typically include numerous product features belonging to the same or different product devices. Each layer of product features or pattern is generally formed using some type of semiconductor patterning process, such as photolithography. Each layer pattern is first formed in a photoresist material that is disposed over a particular semiconductor material. Exposure light is then passed through a mask which forms a design pattern, and the design pattern is then exposed onto the resist material forming an exposed pattern on the resist material. Subsequent development of the exposed resist pattern results in activation of such pattern so that the developed resist pattern can be used during an etching process to prevent the underlying semiconductor material from being etched away while the exposed semiconductor material is etched away, or visa versa. Thus, the semiconductor material underlying the resist pattern areas (or the areas outside the resist pattern) is patterned to form product features.
Patterning processes (e.g., photolithography) are becoming very challenging as the feature sizes go below the standard resolution limit of the patterning tool. One challenge includes achieving an accurate transfer of the design features into final patterned features. Resolution enhancement techniques (RETs) are used to achieve a smaller resolution on the patterned material (e.g., photoresist or device layer) than the actual resolution of the mask used to form the resulting pattern. Additionally, the limits of optical imaging technology as a vehicle for semiconductor patterning are being pushed. By way of example, when a 70 nm line width is to be patterned on a 200 nm pitch using an exposure tool having a Numerical Aperture NA=0.75 and wavelength of about 193 nm, the k1 factor will be related to the tool by the equation:Minimum half pitch=k1λ/NA 
Thus, k1 will be 0.39. Under these conditions, imaging behavior is complex. As a result, the range of feature dimensions that are potentially at risk of being outside the bounds of process control and which constitute a yield risk grows rapidly as k1 diminishes. Furthermore, the risks are often associated with the combined effects of pattern shifts with shape changes.
Another challenge as pattern sizes become smaller is that it is often difficult (or impossible) to measure the small features using conventional optical tools. Alternatively, a scanning electron microscopy (SEM) system can be used to analyze the integrity of the small features. However, SEM systems require a significant amount of time to load and seal the wafer into the vacuum and then to acquire the high resolution image using the SEM. Thus, it is difficult to efficiently determine whether particular feature characteristics, such as shape or location fidelity, are within specification or are likely to fail using conventional optical and SEM inspection techniques.
In light of the foregoing, improved mechanisms for monitoring feature fidelity or for monitoring the fidelity of processes for fabricating features are needed.